`include "defines.v"
module ysyx_210448_cpu_abtiter(
  input wire clk,
  input wire rst,
  input wire exe_pc_write,
  input wire [63:0] exe_pc_add,
  input wire csr_pc_write,
  input wire [63:0] csr_pc_add,
  input wire [31:0] if_inst,
  input wire axi_mem_read,
  input wire mem_read,
  input wire if_ar_valid,
  input wire [3:0]if_read_id,
  input wire [3:0]mem_read_id,
  input wire [3:0]axi_r_id_i,
  input wire [3:0] axi_r_id,
  input wire r_hs,
  input wire wb_read,
  input wire [63:0] r_data,
  input wire [63:0] if_addr,
  input wire [63:0] mem_read_addr,
  input wire axi_read_ready,
  input  wire [63:0] axi_data_read,
  output wire [63:0] if_read_data,
  output wire [63:0] mem_read_data,
  output  wire axi_read_valid,
  output reg [63:0] axi_addr,
  output wire [1:0] axi_size,
  output wire handshake_done,
  output wire [3:0] axi_id,
  output wire stop,
  output wire pc_write,
  output wire [63:0] pc_add,
  output wire mem_wb_en,
  output wire mem_read_close
);

assign axi_read_valid=((if_inst==32'b0)&&(exe_pc_write==1'b1))?0:((axi_mem_read)?mem_read:if_ar_valid);
assign handshake_done=(axi_read_valid)&&(axi_read_ready);//不必要的

assign stop=(mem_read)?((wb_read&&axi_r_id_i==4'b0010)?1'b0:1'b1):(1'b0);//wb_read

assign mem_wb_en=(mem_read)?((axi_r_id_i==4'b0001)?1'b1:1'b0):1'b1;//axi_r_id==4'b0010&&r_hs
assign mem_read_close=(axi_r_id_i==4'b0001)?1:0;//
assign if_read_data=(axi_r_id_i==4'b0010)?axi_data_read:0;
assign mem_read_data=(axi_r_id_i==4'b0001)?r_data:0;


always @(*) begin
  if (rst) begin
    axi_addr=64'b0;
    axi_id=4'b0;
  end
  else 
  if(axi_mem_read&&~mem_read_close)
  begin
      axi_addr=mem_read_addr;
      axi_id=mem_read_id;
  end
  else
  begin
    begin
      axi_addr=if_addr;
      axi_id=if_read_id;
    end
  end
  if(csr_pc_write)
  begin
    pc_write=csr_pc_write;
    pc_add=csr_pc_add;
  end
  else
  begin
    pc_write=exe_pc_write;
    pc_add=exe_pc_add;
  end
    
end


assign axi_size = `SIZE_W;

endmodule
